In contrast to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs), which are fabricated using conventional lithographic fabrication methods, non-planar FETs incorporate various vertical transistor structures. One such transistor structure is the “FinFET,” which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels, and which are typically on the order of tens of nanometers in width.
A FinFET is a type of transistor that can be fabricated using very small scale processes. FIG. 1 is a simplified perspective view of a FinFET 100, which is formed on a semiconductor wafer substrate 102. As shown in FIG. 1, each fin 104 extends between a source region 106 and a drain region 108 of FinFET 100. FinFET 100 includes a gate structure 110 that is formed across fins 104. The gate structure 110 typically includes multiple layers of gate electrode (conducting materials) and gate dielectric (high-k) (not shown in FIG. 1). The surface area of the fins 104 in contact with gate structure 110 determines the effective channel of FinFET 100.
Similar to planar transistors, source and drain silicide layers may be formed on the source and drain regions 106, 108 of FinFET 100. However, since the fins 104 of FinFETs such as FinFET 100 are typically narrow, current crowding may occur. In addition, it is difficult to land contact plugs onto the source/drain 106, 108 portions of the fins 104. One known solution to alleviate this problem is the formation of epitaxial semiconductor layers on the fins to increase their volumes using known epitaxy processes.
In one known example, selective epitaxial growth (SEG) technology may be employed. In the prior art, SEG technology has been widely used at 32 nm node and beyond in planar CMOS technology. The SEG is performed on source/drain areas using, for example, SiGe for p-type transistors and Si:C for n-type transistors. SEG is typically performed after polysilicon gate and spacer formation (in gate first flow processes) or before replacement gate (RMG) formation (in gate last flow processes). SEG is beneficially employed for stress engineering (i.e. to enhance electron mobility) and also for lower source/drain resistance. In known SEG process, silicon atoms only nucleate and grow on a silicon surface (and not on a silicon oxide or nitride surface) by using a single-wafer process chamber (at reduced pressure, for example less than 50 Torr, and at reduced temperature, for example less than 600° C.) with SiCl2H2 or SiCl4/H2, for example, as precursor gases. The precursor gasses can also be mixed with some percentage of germanium for SiGe growth, or dopants (e.g., C, B, P, and/or As) for in-situ doping.
The epitaxial processes (SEG), however, suffer from drawbacks. FIG. 2 illustrates a cross-sectional view of a semiconductor structure including source (or alternatively drain) region (which also includes part of the original fin 104) and epitaxy layer 106a epitaxially grown on the source/drain region at fin 104. In contrast to conventional planar devices, the volumes of source/drain regions are not confined by shallow trench isolation (STI) regions 116. Since epitaxy layer 106a may have a growth rate smaller on (111) planes than on other planes, the outer surface of epitaxy layer 106a may not have a rectangular (or near-rectangular) profile as that of the original fin 104. Instead, epitaxy layer 106a may extend laterally and form facets 118 (typically the (111) plane of Si). This may cause a reduction in the distance between epitaxy layers grown from neighboring fins, as becomes more apparent in FIG. 3 wherein two fins are illustrated. Accordingly, the amount of SEG in which the epitaxially grown layers growing from neighboring fins will not merge is reduced.
Again, the exposed source/drain region of the fins, using SEG in a FinFET architecture, is grown larger (laterally and vertically) into diamond shape due to slower epitaxial silicon growth on the (111) surface. Thus, for a given fin-pitch, there is a trade-off between the amount of SEG able to be grown on the source/drain regions (for stress engineering and low resistance) and the amount of spacing adjacent to the source/drain regions of the fins (for avoiding electrical short). Referring to FIG. 4, this problem becomes particularly apparent in the context of alternatively doped adjacent fins, after a silicide layer 112 is deposited. As shown therein, a short would result due to the adjacency of the silicide layer 112 over neighboring n-type and p-type doped source/drain regions.
One solution to this problem know in the prior art describes methods to control the source/drain profile after SEG by performing an in-situ etch cycle (by adding etching gases, e.g. HCl) in the same SEG chamber without breaking the vacuum. See Su et al., United States Patent Application Publication no. 2011/0210404 A1, published on Sep. 1, 2011, and entitled “Epitaxy Profile Engineering for FinFETs.” As illustrated therein, just two cycles of SEG-etch-SEG-etch can result in ellipse shape (or egg shape) of the fins, and desirably result in smaller lateral growth in subsequent SEG steps.
Accordingly, it is desirable to provide improved methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings, the brief summary, and this background of the invention.